2n5564/5565/5566 vishay siliconix document number: 70254 s-50150?rev. e, 24-jan-05 www.vishay.com 1 matched n-channel jfet pairs product summary part number v gs(off) (v) v (br)gss min (v) g fs min (ms) i g typ (pa) v gs1 ? v gs2 max (mv) 2n5564 ? 0.5 to ? 3 ? 40 7.5 ? 3 5 2n5565 ? 0.5 to ? 3 ? 40 7.5 ? 3 10 2n5566 ? 0.5 to ? 3 ? 40 7.5 ? 3 20 features benefits applications two-chip design high slew rate low offset/drift voltage low gate leakage: 3 pa low noise: 12 nv ? hz @ 10 hz good cmrr: 76 db minimum parasitics tight differential match vs. current improved op amp speed, settling time accuracy minimum input error/trimming requirement insignificant signal loss/error voltage high system sensitivity minimum error with large input signals maximum high frequency performance wideband differential amps high-speed, temp-compensated, single-ended input amps high-speed comparators impedance converters matched switches description the 2n5564/5565/5566 are matched pairs of jfets mounted in a to-71 package. this two-chip design reduces parasitics for good performance at high frequency while ensuring extremely tight matching. this series features high breakdown voltage (v (br)dss typically > 55 v), high gain (typically > 9 ms), and <5 mv offset between the two die. the hermetically-sealed to-71 package is available with full military processing (see military information). for similar products see the low-noise u/sst401 series, and the low-leakage 2n5196/5197/5198/5199 data sheets. to-71 top view g 1 s 1 d 1 g 2 d 2 s 2 1 2 3 6 5 4 absolute maximum ratings gate-drain, gate-source voltage ? 40 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gate-gate voltage 80 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gate current 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead tempe rature ( 1 / 16 ? from case for 10 sec.) 300 c . . . . . . . . . . . . . . . . . . storage temperature ? 65 to 200 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction t emperature ? 55 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation : per side a 325 mw . . . . . . . . . . . . . . . . . . . . . . . . total b 650 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. derate 2.6 mw/ c above 25 c b. derate 5.2 mw/ c above 25 c
2n5564/5565/5566 vishay siliconix www.vishay.com 2 document number: 70254 s-50150?rev. e, 24-jan-05 specifications (t a = 25 c unless otherwise noted) limits 2n5564 2n5565 2n5566 parameter symbol test conditions typ a min max min max min max unit static gate-source breakdown voltage v (br)gss i g = ? 1 a, v ds = 0 v ? 55 ? 40 ? 40 ? 40 v gate-source cutoff voltage v gs(off) v ds = 15 v, i d = 1 na ? 2 ? 0.5 ? 3 ? 0.5 ? 3 ? 0.5 ? 3 v saturation drain current b i dss v ds = 15 v, v gs = 0 v 20 5 30 5 30 5 30 ma gate reverse current i gss v gs = ? 20 v, v ds = 0 v ? 5 ? 100 ? 100 ? 100 pa gate reverse current i gss t a = 150 c ? 10 ? 200 ? 200 ? 200 na gate operating current c i g v dg = 15 v, i d = 2 ma ? 3 pa gate operating current c i g t a = 125 c ? 1 na drain-source on-resistance r ds(on) v gs = 0 v, i d = 1 ma 50 100 100 100 gate-source v oltage c v gs v dg = 15 v, i d = 2 ma ? 1.2 gate-source forward voltage v gs(f) i g = 2 ma , v ds = 0 v 0.7 1 1 1 v dynamic common-source forward t ransconductance g fs v ds = 15 v, i d = 2 ma 9 7.5 12.5 7.5 12.5 7.5 12.5 ms common-source output conductance g os v ds = 15 v , i d = 2 ma f = 1 khz 35 45 45 45 s common-source forward t ransconductance d g fs v ds = 15 v, i d = 2 ma f = 100 mhz 8.5 7 7 7 ms common-source input capacitance c iss v ds = 15 v i d = 2 ma 10 12 12 12 common-source reverse t ransfer capacitance c rss v ds = 15 v, i d = 2 ma f = 1 mhz 2.5 3 3 3 pf equivalent input noise voltage e n v ds = 15 v, i d = 2 ma f = 10 hz 12 50 50 50 nv ? hz noise figure nf r g = 10 m 1 1 1 db matching differential gate-source v oltage | v gs1 ?v gs2 | v dg = 15 v, i d = 2 ma 5 10 20 mv gate-source v oltage differential change with temperature | v gs1 ?v gs2 | t v dg = 15 v, i d = 2 ma t a = ? 55 to 125 c 10 25 50 v/ c saturation drain current ratio c i dss1 i dss2 v ds = 15 v, v gs = 0 v 0.98 0.95 1 0.95 1 0.95 1 transconductance ratio g fs1 g fs2 v ds = 15 v, i d = 2 ma f = 1 khz 0.98 0.95 1 0.90 1 0.90 1 common mode rejection ratio c cmrr v dg = 10 to 20 v i d = 2 ma 76 db notes a. typical values are for design aid only, not guaranteed nor subject to production testing. ncbd b. pulse test: pw 300 s duty cycle 3%. c. this parameter not registered with jedec. d. not a production test. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2n5564/5565/5566 vishay siliconix document number: 70254 s-50150?rev. e, 24-jan-05 www.vishay.com 3 typical characteristics (t a = 25 c unless otherwise noted) on-resistance and drain current vs. gate-source cutoff voltage on-resistance vs. drain current 100 0 ? 10 0 200 160 0 r ds i dss r ds @ id = 1 ma, v gs = 0 i dss @ v ds = 15 v, v gs = 0 100 0 1 10 100 v gs(off) = ? 2 v t a = 25 c v gs(off) ? gate-source cutoff voltage (v) i d ? drain current (ma) 80 60 40 20 80 60 40 20 ? 2 ? 4 ? 6 ? 8 120 80 40 turn-on switching 5 0 ? 10 4 3 2 1 0 t r switching time (ns) t d(on) @ i d = 3 ma t d(on) @ i d = 12 ma t r approximately independent of i d v dg = 5 v, r g = 50 v gs(l) = ? 10 v v gs(off) ? gate-source cutoff voltage (v) ? 2 ? 4 ? 6 ? 8 turn-off switching 30 010 24 18 12 6 0 v gs(off) = ? 2 v t d(off) t d(off) independent of device v gs(off) v dg = 5 v, v gs(l) = ? 10 v i d ? drain current (ma) 24 68 switching time (ns) forward transconductance and output conductance vs. gate-source cutoff voltage 50 0 0 ? 2 ? 10 500 200 0 g fs ? forward transconductance (ms) g fs g os g fs and g os @ v ds = 15 v v gs = 0 v, f = 1 khz v gs(off) ? gate-source cutoff voltage (v) 40 30 20 10 ? 4 ? 6 ? 8 400 200 100 160 120 on-resistance vs. temperature 200 ? 55 25 125 0 ? 15 85 i d = 1 ma r ds changes 0.7%/ c v gs(off) = ? 2 v t a ? temperature ( c) 80 40 ? 35 5 45 65 105 t f r ds(on) ? drain-source on-resistance ( ) r ds(on) ? drain-source on-resistance ( ) r ds(on) ? drain-source on-resistance ( ) ? saturation drain current (ma) i dss s) g os ? output conductance (
2n5564/5565/5566 vishay siliconix www.vishay.com 4 document number: 70254 s-50150?rev. e, 24-jan-05 typical characteristics (t a = 25 c unless otherwise noted) 40 32 24 16 8 0 0 ? 0.4 ? 0.8 ? 1.2 ? 1.6 ? 2 v ds = 15 v ? drain current (ma) i d v gs ? gate-source voltage (v) t a = ? 55 c 25 c 125 c transfer characteristics 14 12 10 8 6 4 2 0 0 4 8 12 16 20 output characteristics v ds ? drain-source voltage (v) ? drain current (ma) i d v gs(off) = ? 1.5 v v gs = 0 v ? 0.1 v ? 0.2 v ? 0.3 v ? 0.4 v ? 0.5 v ? 0.6 v ? 0.7 v output characteristics v ds ? drain-source voltage (v) ? drain current (ma) i d 5 01 0.8 0.6 0.4 0.2 4 3 2 0 1 v gs(off) = ? 1.5 v ? 0.2 v ? 0.3 v ? 0.4 v ? 0.5 v ? 0.6 v ? 0.7 v ? 0.8 v ? 0.9 v capacitance vs. gate-source voltage 30 ? 20 24 18 12 6 0 capacitance (pf) f = 1 mhz v ds = 0 v c iss c rss 0 v gs ? gate-source voltage (v) ? 4 ? 8 ? 12 ? 16 gate leakage current 030 ? gate leakage i g t a = 125 c t a = 25 c 1 ma i gss @ 25 c i d = 10 ma common-gate input admittance 100 10 1 0.1 100 1000 200 500 (ms) g ig b ig v dg = 15 v i d = 10 ma t a = 25 c v dg ? drain-gate voltage (v) f ? frequency (mhz) i gss @ 25 c 10 ma 1 ma 6 121824 i g(on) @ i d 0.1 pa 1 pa 10 pa 100 pa 1 na 10 na ? 0.1 v v gs(off) = ? 2 v v gs = 0 v
2n5564/5565/5566 vishay siliconix document number: 70254 s-50150?rev. e, 24-jan-05 www.vishay.com 5 typical characteristics (t a = 25 c unless otherwise noted) common-gate forward admittance common-gate reverse admittance 100 10 1 0.1 100 1000 200 500 (ms) ? g fg b fg g fg v dg = 15 v i d = 10 ma t a = 25 c 10 1 0.1 0.01 100 1000 200 500 v dg = 15 v i d = 10 ma t a = 25 c ? g rg ? b rg +g rg (ms) f ? frequency (mhz) f ? frequency (mhz) common-gate output admittance 100 10 1 0.1 100 1000 200 500 (ms) v dg = 15 v i d = 10 ma t a = 25 c g og b og f ? frequency (mhz) noise voltage vs. frequency 100 10 1 10 100 1 k 100 k 10 k i d = 1 ma i d = 10 ma v ds = 15 v f ? frequency (hz) transconductance vs. drain current 100 10 1 0.1 1.0 10 i d ? drain current (ma) t a = ? 55 c 25 c 125 c output conductance vs. drain current 1000 100 10 0.1 1.0 10 i d ? drain current (ma) t a = ? 55 c 25 c 125 c v ds = 15 v f = 1 khz v gs(off) = ? 2 v v ds = 15 v f = 1 khz v gs(off) = ? 2 v e n ? noise voltage nv / hz g os ? output conductance ( s) g fs ? forward transconductance (ms) vishay siliconix maintains worldw ide manufacturing capability. pr oducts may be manufactured at on e of several q ualified locati ons. reliability data fo r silicon te chnology and package reliability represent a co mposite of all qualifie d locations. for relate d documents such as pa ckage/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?70254 .
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